Difference between revisions of "PLD Workshop 04 06 2013"
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| + | Get the slides, [[File:Pld-1.2-intro-and-tooling.pdf]] ! | ||
==== Tooling, VHDL/Verilog basics ==== | ==== Tooling, VHDL/Verilog basics ==== | ||
* Xilinx tooling (we'll use it, try to have it installed) | * Xilinx tooling (we'll use it, try to have it installed) | ||
** http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html (*ISE*, _not_ Vivado) | ** http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html (*ISE*, _not_ Vivado) | ||
| + | ** ftp://ftp.hsgr.awmn/upload/Xilinx_ISE_DS_Lin_14.5_P.58f_4.tar (Linux, Internal hsgr/awmn link) | ||
| + | ** ftp://ftp.hsgr.awmn/upload/Xilinx_ISE_DS_Win_14.5_P.58f_4.tar (Windows, Internal hsgr/awmn link) | ||
| + | ** (You still have to register to get a free WebISE license) | ||
* VHDL & Verilog introduction | * VHDL & Verilog introduction | ||
** Design goals, short history | ** Design goals, short history | ||
* Verilog syntax & examples | * Verilog syntax & examples | ||
** We'll do some hands on basic stuff on our h/w ! | ** We'll do some hands on basic stuff on our h/w ! | ||
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| + | Don't forget to bring your own laptop | ||
Also checkout [[Programmable_Logic_Lessons|The main page]] | Also checkout [[Programmable_Logic_Lessons|The main page]] | ||
Latest revision as of 01:11, 4 June 2013
 [Hackerspace.gr external link] |
Starts | Organizer |
|---|---|---|
| Tue 04 Jun 2013 19:00 | Hackerspace.gr | |
| Ends | Event Owner | |
| Tue 04 Jun 2013 21:00 | User:Skmp |
Switches! Lots of them!
Get the slides, File:Pld-1.2-intro-and-tooling.pdf !
Tooling, VHDL/Verilog basics
- Xilinx tooling (we'll use it, try to have it installed)
- http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html (*ISE*, _not_ Vivado)
- ftp://ftp.hsgr.awmn/upload/Xilinx_ISE_DS_Lin_14.5_P.58f_4.tar (Linux, Internal hsgr/awmn link)
- ftp://ftp.hsgr.awmn/upload/Xilinx_ISE_DS_Win_14.5_P.58f_4.tar (Windows, Internal hsgr/awmn link)
- (You still have to register to get a free WebISE license)
- VHDL & Verilog introduction
- Design goals, short history
- Verilog syntax & examples
- We'll do some hands on basic stuff on our h/w !
Don't forget to bring your own laptop
Also checkout The main page
