Difference between revisions of "PLD Workshop 2013/10/02"
From Hackerspace.gr
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''verilog WIP @ [https://github.com/pld-lessons/simple_soc/tree/master/src/fpga/verilog_core github]'' | ''verilog WIP @ [https://github.com/pld-lessons/simple_soc/tree/master/src/fpga/verilog_core github]'' | ||
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==== Plans for the workshop ==== | ==== Plans for the workshop ==== | ||
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* Attach vga logic | * Attach vga logic | ||
| + | ==== Aftermath ==== | ||
| + | * Implemented ram using built in, block ram | ||
| + | * Added state logic for ram delays | ||
Also checkout [[Simple_SoC|The main project page]] | Also checkout [[Simple_SoC|The main project page]] | ||
Latest revision as of 13:18, 3 October 2013
 [Hackerspace.gr external link] |
Starts | Organizer |
|---|---|---|
| Wed 02 Oct 2013 19:30 | Hackerspace.gr | |
| Ends | Event Owner | |
| Wed 02 Oct 2013 21:30 | User:Skmp |
Howdy Simulator
Stuff for review
sdlcore @ github
verilog WIP @ github
Plans for the workshop
- Work a bit on the verilog code
- Load example program
- Simulate it
- Attach vga logic
Aftermath
- Implemented ram using built in, block ram
- Added state logic for ram delays
Also checkout The main project page
