Difference between revisions of "PLD Workshop 2013/10/23"
From Hackerspace.gr
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''verilog WIP @ [https://github.com/pld-lessons/simple_soc/tree/master/src/fpga/verilog_core github]'' | ''verilog WIP @ [https://github.com/pld-lessons/simple_soc/tree/master/src/fpga/verilog_core github]'' | ||
| + | |||
| + | ==== aftermath ==== | ||
| + | * Fixed vga output, centered, with colored border | ||
| + | * Debugged the vram contents & vga out on the simulator, everything seems fine | ||
| + | * Actuall hardware still glitched | ||
==== ideas for the workshop ==== | ==== ideas for the workshop ==== | ||
Latest revision as of 23:40, 23 October 2013
 [Hackerspace.gr external link] |
Starts | Organizer |
|---|---|---|
| Wed 23 Oct 2013 19:30 | Hackerspace.gr | |
| Ends | Event Owner | |
| Wed 23 Oct 2013 21:30 | User:Skmp |
We love glitches
Stuff for review
sdlcore @ github
verilog WIP @ github
aftermath
- Fixed vga output, centered, with colored border
- Debugged the vram contents & vga out on the simulator, everything seems fine
- Actuall hardware still glitched
ideas for the workshop
- Fix core/vram/vga to get some real video output!
- See if we can fit the vram by resizing things?
Also checkout The main project page
