Difference between revisions of "PLD Workshop 2013/11/06"

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''verilog WIP @ [https://github.com/pld-lessons/simple_soc/tree/master/src/fpga/verilog_core github]''
 
''verilog WIP @ [https://github.com/pld-lessons/simple_soc/tree/master/src/fpga/verilog_core github]''
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==== aftermath ====
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* designed an ICE protocol to ease debugging
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* Investigated UART
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** Tested echo implementation at 3MBaud, worked nicely
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* Investigated ISA
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** 6 mhz looks plausible for interfacing (VGA/ETH)
  
 
==== ideas for the workshop ====
 
==== ideas for the workshop ====

Latest revision as of 22:22, 13 November 2013

Simple soc logo.jpg

[Hackerspace.gr external link]
Starts Organizer
Wed 13 Nov 2013 19:30 Hackerspace.gr
Ends Event Owner
Wed 13 Nov 2013 21:30 User:Skmp

Differential debugging




Stuff for review

sdlcore @ github

verilog WIP @ github

aftermath

  • designed an ICE protocol to ease debugging
  • Investigated UART
    • Tested echo implementation at 3MBaud, worked nicely
  • Investigated ISA
    • 6 mhz looks plausible for interfacing (VGA/ETH)

ideas for the workshop

  • think ways to update the program
    • this is a must so we can test/develop faster
  • Test/design validation "suite"?
  • See why the simple tests don't work on the hardware
    • But they work on the xilinx simulator. Some kind of corner case?
  • take pictures
  • cleanup repo ?


Also checkout The main project page