Difference between revisions of "Simple SoC"

From Hackerspace.gr
Jump to: navigation, search
 
(24 intermediate revisions by 2 users not shown)
Line 9: Line 9:
 
We'll merely keep a meetup log and notes here, important stuff will be stored in One Single Repo (tm), next to the code :)
 
We'll merely keep a meetup log and notes here, important stuff will be stored in One Single Repo (tm), next to the code :)
  
−
== Meetups ==
 
  
−
=== Upcoming ===
+
(Final?) working implementation, with VGA output and debugger
  
−
==== [[PLD_Workshop_2013/10/23|2013/10/23 - We love glitches]] ====
+
https://www.youtube.com/watch?v=YfNVco7CpEU
−
* Fix core/vram/vga to get some real video output!
+
−
* See if we can fit the vram by resizing things?
+
  
−
=== Log ===
+
== Meetup Log ==
  
−
==== [[PLD_Workshop_2013/10/16|2013/10/16 - How about conditions?]] ====
+
==== [[PLD_Workshop_11_09_2013|2013/09/11 - September reunion]] ====
−
* Implemented beq, bga, bgt, jr, draw, fix write16, read16
+
* Discuss and improve specs a bit
−
* wires up vram (resized to 2bpp because it doesn't fit)
+
* Update documentation and C# ref. implementation
−
* added vga output, but it is glitched/buggy
+
* forked from [[Programmable Logic Lessons]] to [[Simple SoC]]
 +
 
 +
==== [[PLD_Workshop_18_09_2013|2013/09/18 - Let there be code]] ====
 +
* Debugged & Finished sdlcore implementation
 +
 
 +
==== [[PLD_Workshop_2013/09/25|2013/09/25 - Verilog at last]] ====
 +
* Spec now has vsync
 +
* Reviewed sdlcore code
 +
* Hacked together some very basic Verilog
 +
 
 +
==== [[PLD_Workshop_2013/10/02|2013/10/02 - Howdy Simulator]] ====
 +
* Implemented ram
 +
* Added delays for ram
  
 
==== [[PLD_Workshop_2013/10/09|2013/10/09 - Howdy Simulator, for real]] ====
 
==== [[PLD_Workshop_2013/10/09|2013/10/09 - Howdy Simulator, for real]] ====
Line 29: Line 38:
 
* cpu mostly works, needs some more opcodes!
 
* cpu mostly works, needs some more opcodes!
  
−
==== [[PLD_Workshop_2013/10/02|2013/10/02 - Howdy Simulator]] ====
+
==== [[PLD_Workshop_2013/10/16|2013/10/16 - How about conditions?]] ====
−
* Implemented ram
+
* Implemented beq, bga, bgt, jr, draw, fixed write16, read16
−
* Added delays for ram
+
* wired up vram (resized to 2bpp because it doesn't fit)
 +
* added vga output, but it is glitched/buggy
  
−
==== [[PLD_Workshop_2013/09/25|2013/09/25 - Verilog at last]] ====
+
==== [[PLD_Workshop_2013/10/23|2013/10/23 - We love glitches]] ====
−
* Spec now has vsync
+
* Fixed VGA, centered image, still outputs corrupted data though
−
* Reviewed sdlcore code
+
* vram resized to 256x256x3 in order to fit
−
* Hacked together some very basic Verilog
+
  
−
==== [[PLD_Workshop_18_09_2013|2013/09/18 - Let there be code]] ====
+
==== [[PLD_Workshop_2013/10/30|2013/10/30 - Corrupted Pixels]] ====
−
* Debugged & Finished sdlcore implementation
+
* Had no luck actually locating the vga corruption bug
 +
* simulator results and simpler test cases seem to work fine
 +
* implemented wait
  
−
==== [[PLD_Workshop_11_09_2013|2013/09/11 - September reunion]] ====
+
==== [[PLD_Workshop_2013/11/06|2013/11/13 - Differential debugging]] ====
−
* Discuss and improve specs a bit
+
* Investigate serial communications
−
* Update documentation and C# ref. implementation
+
* Try out UART sample
−
* forked from [[Programmable Logic Lessons]] to [[Simple SoC]]
+
* draft out ICE spec
 +
 
 +
==== [[PLD_Workshop_2013/11/20|2013/11/20 - Want some ICE?]] ====
 +
* *almost* implemented the UART
 +
* We have some pin collisions on clock vs dcm vs io-standards per ban
 +
 
 +
==== [[PLD_Workshop_2.10|2013/12/04 - Clocks and IO]] ====
 +
* Worked around the IO/DCM issues
 +
* WIP on the ICE implementation
 +
 
 +
==== [[PLD_Workshop_2.11|2013/12/11 - Debuggable Hardware]] ====
 +
* Work on the ICE implementation
 +
 
 +
==== [[PLD_Workshop_2.12|2014/01/22 - ICEful modules]] ====
 +
* Modularization, refactoring
 +
 
 +
==== [[PLD_Workshop_2.13|2014/01/29 - Making it work once more]] ====
 +
* Get the modularised code back into working state
 +
* implement some of the ICE state machine
 +
 
 +
==== [[PLD_Workshop_2.14|2014/02/05 - Debugger Integration]] ====
 +
* implement some of the ICE state machine
 +
* have it talk nicely with the debugger
 +
* -> We got VGA writes working!
 +
 
 +
==== [[PLD_Workshop_2.15|2014/02/26 - Wait States]] ====
 +
* Add wait states for ICE & module integration on the cpu
 +
* have it talk nicely with the debugger
  
 
== Resources ==
 
== Resources ==
Line 50: Line 88:
 
** Direct links, [https://github.com/pld-lessons/slides slides], [https://github.com/pld-lessons/vga_out vga_out verilog example], [https://github.com/pld-lessons/simple_cpu a simple cpu in C]
 
** Direct links, [https://github.com/pld-lessons/slides slides], [https://github.com/pld-lessons/vga_out vga_out verilog example], [https://github.com/pld-lessons/simple_cpu a simple cpu in C]
 
* Your favorite search engine
 
* Your favorite search engine
 +
 +
[[Category:Projects]]

Latest revision as of 00:15, 13 June 2018

Description

A very basic, custom SoC softcore


Primary git repo: on github

Specs/Design: on github as well

We'll merely keep a meetup log and notes here, important stuff will be stored in One Single Repo (tm), next to the code :)


(Final?) working implementation, with VGA output and debugger

https://www.youtube.com/watch?v=YfNVco7CpEU

Meetup Log

2013/09/11 - September reunion

  • Discuss and improve specs a bit
  • Update documentation and C# ref. implementation
  • forked from Programmable Logic Lessons to Simple SoC

2013/09/18 - Let there be code

  • Debugged & Finished sdlcore implementation

2013/09/25 - Verilog at last

  • Spec now has vsync
  • Reviewed sdlcore code
  • Hacked together some very basic Verilog

2013/10/02 - Howdy Simulator

  • Implemented ram
  • Added delays for ram

2013/10/09 - Howdy Simulator, for real

  • debug, debug, debug, and simulate
  • Implemented more state logic
  • cpu mostly works, needs some more opcodes!

2013/10/16 - How about conditions?

  • Implemented beq, bga, bgt, jr, draw, fixed write16, read16
  • wired up vram (resized to 2bpp because it doesn't fit)
  • added vga output, but it is glitched/buggy

2013/10/23 - We love glitches

  • Fixed VGA, centered image, still outputs corrupted data though
  • vram resized to 256x256x3 in order to fit

2013/10/30 - Corrupted Pixels

  • Had no luck actually locating the vga corruption bug
  • simulator results and simpler test cases seem to work fine
  • implemented wait

2013/11/13 - Differential debugging

  • Investigate serial communications
  • Try out UART sample
  • draft out ICE spec

2013/11/20 - Want some ICE?

  • *almost* implemented the UART
  • We have some pin collisions on clock vs dcm vs io-standards per ban

2013/12/04 - Clocks and IO

  • Worked around the IO/DCM issues
  • WIP on the ICE implementation

2013/12/11 - Debuggable Hardware

  • Work on the ICE implementation

2014/01/22 - ICEful modules

  • Modularization, refactoring

2014/01/29 - Making it work once more

  • Get the modularised code back into working state
  • implement some of the ICE state machine

2014/02/05 - Debugger Integration

  • implement some of the ICE state machine
  • have it talk nicely with the debugger
  • -> We got VGA writes working!

2014/02/26 - Wait States

  • Add wait states for ICE & module integration on the cpu
  • have it talk nicely with the debugger

Resources

Retrieved from "https://www.hackerspace.gr/wiki/index.php?title=Simple_SoC&oldid=80559"