Difference between revisions of "Simple SoC"
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| − | + | == Description == | |
| − | A very basic SoC | + | A very basic, custom [http://en.wikipedia.org/wiki/System_on_a_chip SoC] [http://en.wikipedia.org/wiki/Soft_microprocessor softcore] |
| Line 9: | Line 9: | ||
We'll merely keep a meetup log and notes here, important stuff will be stored in One Single Repo (tm), next to the code :) | We'll merely keep a meetup log and notes here, important stuff will be stored in One Single Repo (tm), next to the code :) | ||
| − | |||
| − | + | (Final?) working implementation, with VGA output and debugger | |
| − | + | https://www.youtube.com/watch?v=YfNVco7CpEU | |
| − | == | + | == Meetup Log == |
| − | === [[ | + | ==== [[PLD_Workshop_11_09_2013|2013/09/11 - September reunion]] ==== |
* Discuss and improve specs a bit | * Discuss and improve specs a bit | ||
* Update documentation and C# ref. implementation | * Update documentation and C# ref. implementation | ||
| + | * forked from [[Programmable Logic Lessons]] to [[Simple SoC]] | ||
| + | ==== [[PLD_Workshop_18_09_2013|2013/09/18 - Let there be code]] ==== | ||
| + | * Debugged & Finished sdlcore implementation | ||
| − | === | + | ==== [[PLD_Workshop_2013/09/25|2013/09/25 - Verilog at last]] ==== |
| − | * The material from [[ | + | * Spec now has vsync |
| + | * Reviewed sdlcore code | ||
| + | * Hacked together some very basic Verilog | ||
| + | |||
| + | ==== [[PLD_Workshop_2013/10/02|2013/10/02 - Howdy Simulator]] ==== | ||
| + | * Implemented ram | ||
| + | * Added delays for ram | ||
| + | |||
| + | ==== [[PLD_Workshop_2013/10/09|2013/10/09 - Howdy Simulator, for real]] ==== | ||
| + | * debug, debug, debug, and simulate | ||
| + | * Implemented more state logic | ||
| + | * cpu mostly works, needs some more opcodes! | ||
| + | |||
| + | ==== [[PLD_Workshop_2013/10/16|2013/10/16 - How about conditions?]] ==== | ||
| + | * Implemented beq, bga, bgt, jr, draw, fixed write16, read16 | ||
| + | * wired up vram (resized to 2bpp because it doesn't fit) | ||
| + | * added vga output, but it is glitched/buggy | ||
| + | |||
| + | ==== [[PLD_Workshop_2013/10/23|2013/10/23 - We love glitches]] ==== | ||
| + | * Fixed VGA, centered image, still outputs corrupted data though | ||
| + | * vram resized to 256x256x3 in order to fit | ||
| + | |||
| + | ==== [[PLD_Workshop_2013/10/30|2013/10/30 - Corrupted Pixels]] ==== | ||
| + | * Had no luck actually locating the vga corruption bug | ||
| + | * simulator results and simpler test cases seem to work fine | ||
| + | * implemented wait | ||
| + | |||
| + | ==== [[PLD_Workshop_2013/11/06|2013/11/13 - Differential debugging]] ==== | ||
| + | * Investigate serial communications | ||
| + | * Try out UART sample | ||
| + | * draft out ICE spec | ||
| + | |||
| + | ==== [[PLD_Workshop_2013/11/20|2013/11/20 - Want some ICE?]] ==== | ||
| + | * *almost* implemented the UART | ||
| + | * We have some pin collisions on clock vs dcm vs io-standards per ban | ||
| + | |||
| + | ==== [[PLD_Workshop_2.10|2013/12/04 - Clocks and IO]] ==== | ||
| + | * Worked around the IO/DCM issues | ||
| + | * WIP on the ICE implementation | ||
| + | |||
| + | ==== [[PLD_Workshop_2.11|2013/12/11 - Debuggable Hardware]] ==== | ||
| + | * Work on the ICE implementation | ||
| + | |||
| + | ==== [[PLD_Workshop_2.12|2014/01/22 - ICEful modules]] ==== | ||
| + | * Modularization, refactoring | ||
| + | |||
| + | ==== [[PLD_Workshop_2.13|2014/01/29 - Making it work once more]] ==== | ||
| + | * Get the modularised code back into working state | ||
| + | * implement some of the ICE state machine | ||
| + | |||
| + | ==== [[PLD_Workshop_2.14|2014/02/05 - Debugger Integration]] ==== | ||
| + | * implement some of the ICE state machine | ||
| + | * have it talk nicely with the debugger | ||
| + | * -> We got VGA writes working! | ||
| + | |||
| + | ==== [[PLD_Workshop_2.15|2014/02/26 - Wait States]] ==== | ||
| + | * Add wait states for ICE & module integration on the cpu | ||
| + | * have it talk nicely with the debugger | ||
| + | |||
| + | == Resources == | ||
| + | * The material from [[Programmable Logic Lessons]] | ||
** Direct links, [https://github.com/pld-lessons/slides slides], [https://github.com/pld-lessons/vga_out vga_out verilog example], [https://github.com/pld-lessons/simple_cpu a simple cpu in C] | ** Direct links, [https://github.com/pld-lessons/slides slides], [https://github.com/pld-lessons/vga_out vga_out verilog example], [https://github.com/pld-lessons/simple_cpu a simple cpu in C] | ||
* Your favorite search engine | * Your favorite search engine | ||
| + | |||
| + | [[Category:Projects]] | ||
Latest revision as of 00:15, 13 June 2018
Contents
- 1 Description
- 2 Meetup Log
- 2.1 2013/09/11 - September reunion
- 2.2 2013/09/18 - Let there be code
- 2.3 2013/09/25 - Verilog at last
- 2.4 2013/10/02 - Howdy Simulator
- 2.5 2013/10/09 - Howdy Simulator, for real
- 2.6 2013/10/16 - How about conditions?
- 2.7 2013/10/23 - We love glitches
- 2.8 2013/10/30 - Corrupted Pixels
- 2.9 2013/11/13 - Differential debugging
- 2.10 2013/11/20 - Want some ICE?
- 2.11 2013/12/04 - Clocks and IO
- 2.12 2013/12/11 - Debuggable Hardware
- 2.13 2014/01/22 - ICEful modules
- 2.14 2014/01/29 - Making it work once more
- 2.15 2014/02/05 - Debugger Integration
- 2.16 2014/02/26 - Wait States
- 3 Resources
Description
A very basic, custom SoC softcore
Primary git repo: on github
Specs/Design: on github as well
We'll merely keep a meetup log and notes here, important stuff will be stored in One Single Repo (tm), next to the code :)
(Final?) working implementation, with VGA output and debugger
https://www.youtube.com/watch?v=YfNVco7CpEU
Meetup Log
2013/09/11 - September reunion
- Discuss and improve specs a bit
- Update documentation and C# ref. implementation
- forked from Programmable Logic Lessons to Simple SoC
2013/09/18 - Let there be code
- Debugged & Finished sdlcore implementation
2013/09/25 - Verilog at last
- Spec now has vsync
- Reviewed sdlcore code
- Hacked together some very basic Verilog
2013/10/02 - Howdy Simulator
- Implemented ram
- Added delays for ram
2013/10/09 - Howdy Simulator, for real
- debug, debug, debug, and simulate
- Implemented more state logic
- cpu mostly works, needs some more opcodes!
2013/10/16 - How about conditions?
- Implemented beq, bga, bgt, jr, draw, fixed write16, read16
- wired up vram (resized to 2bpp because it doesn't fit)
- added vga output, but it is glitched/buggy
2013/10/23 - We love glitches
- Fixed VGA, centered image, still outputs corrupted data though
- vram resized to 256x256x3 in order to fit
2013/10/30 - Corrupted Pixels
- Had no luck actually locating the vga corruption bug
- simulator results and simpler test cases seem to work fine
- implemented wait
2013/11/13 - Differential debugging
- Investigate serial communications
- Try out UART sample
- draft out ICE spec
2013/11/20 - Want some ICE?
- *almost* implemented the UART
- We have some pin collisions on clock vs dcm vs io-standards per ban
2013/12/04 - Clocks and IO
- Worked around the IO/DCM issues
- WIP on the ICE implementation
2013/12/11 - Debuggable Hardware
- Work on the ICE implementation
2014/01/22 - ICEful modules
- Modularization, refactoring
2014/01/29 - Making it work once more
- Get the modularised code back into working state
- implement some of the ICE state machine
2014/02/05 - Debugger Integration
- implement some of the ICE state machine
- have it talk nicely with the debugger
- -> We got VGA writes working!
2014/02/26 - Wait States
- Add wait states for ICE & module integration on the cpu
- have it talk nicely with the debugger
Resources
- The material from Programmable Logic Lessons
- Direct links, slides, vga_out verilog example, a simple cpu in C
- Your favorite search engine
