Difference between revisions of "PLD Workshop 2013/09/25"
From Hackerspace.gr
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* Perhaps extend the spec with vsync wait ? (already implemented in sdlcore) | * Perhaps extend the spec with vsync wait ? (already implemented in sdlcore) | ||
* also, new timeslot cus i'm tired of always being late [skmp] | * also, new timeslot cus i'm tired of always being late [skmp] | ||
| + | |||
| + | ==== aftermath ==== | ||
| + | * Vsync wait now implemented | ||
| + | * Fist hands-on hacking with verilog | ||
Also checkout [[Simple_SoC|The main project page]] | Also checkout [[Simple_SoC|The main project page]] | ||
Latest revision as of 13:37, 27 September 2013
 [Hackerspace.gr external link] |
Starts | Organizer |
|---|---|---|
| Wed 25 Sep 2013 19:30 | Hackerspace.gr | |
| Ends | Event Owner | |
| Wed 25 Sep 2013 21:00 | User:Skmp |
Verilog at last
Stuff for review
ISA/SoC, C# WIP project @ github/simple_soc
sdlcore WIP @ github
Plans for the workshop
- Overall design of the verilog implementation
- And write some code for it
- Perhaps extend the spec with vsync wait ? (already implemented in sdlcore)
- also, new timeslot cus i'm tired of always being late [skmp]
aftermath
- Vsync wait now implemented
- Fist hands-on hacking with verilog
Also checkout The main project page
