Difference between revisions of "Simple SoC"
From Hackerspace.gr
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=== Upcoming === | === Upcoming === | ||
| − | * [[PLD_Workshop_2013/ | + | * [[PLD_Workshop_2013/10/02|2013/10/02 - Howdy Simulator]] |
=== Log === | === Log === | ||
| + | |||
| + | ==== [[PLD_Workshop_2013/09/25|2013/09/25 - Verilog at last]] ==== | ||
| + | * Spec now has vsync | ||
| + | * Reviewed sdlcore code | ||
| + | * Hacked together some very basic Verilog | ||
==== [[PLD_Workshop_18_09_2013|2013/09/18 - Let there be code]] ==== | ==== [[PLD_Workshop_18_09_2013|2013/09/18 - Let there be code]] ==== | ||
Revision as of 13:41, 27 September 2013
Contents
Description
A very basic SoC design
Primary git repo: on github
Specs/Design: on github as well
We'll merely keep a meetup log and notes here, important stuff will be stored in One Single Repo (tm), next to the code :)
Meetups
Upcoming
Log
2013/09/25 - Verilog at last
- Spec now has vsync
- Reviewed sdlcore code
- Hacked together some very basic Verilog
2013/09/18 - Let there be code
- Debugged & Finished sdlcore implementation
2013/09/11 - September reunion
- Discuss and improve specs a bit
- Update documentation and C# ref. implementation
Resources
- The material from Programmable_Logic_Lessons
- Direct links, slides, vga_out verilog example, a simple cpu in C
- Your favorite search engine
