Difference between revisions of "Simple SoC"

From Hackerspace.gr
Jump to: navigation, search
Line 20: Line 20:
  
 
==== [[PLD_Workshop_2013/10/16|2013/10/16 - How about conditions?]] ====
 
==== [[PLD_Workshop_2013/10/16|2013/10/16 - How about conditions?]] ====
* Implemented beq, bga, bgt, jr, draw, fix write16, read16
+
* Implemented beq, bga, bgt, jr, draw, fixed write16, read16
 
* wires up vram (resized to 2bpp because it doesn't fit)
 
* wires up vram (resized to 2bpp because it doesn't fit)
 
* added vga output, but it is glitched/buggy
 
* added vga output, but it is glitched/buggy

Revision as of 00:34, 17 October 2013

Description

A very basic, custom SoC softcore


Primary git repo: on github

Specs/Design: on github as well

We'll merely keep a meetup log and notes here, important stuff will be stored in One Single Repo (tm), next to the code :)

Meetups

Upcoming

2013/10/23 - We love glitches

  • Fix core/vram/vga to get some real video output!
  • See if we can fit the vram by resizing things?

Log

2013/10/16 - How about conditions?

  • Implemented beq, bga, bgt, jr, draw, fixed write16, read16
  • wires up vram (resized to 2bpp because it doesn't fit)
  • added vga output, but it is glitched/buggy

2013/10/09 - Howdy Simulator, for real

  • debug, debug, debug, and simulate
  • Implemented more state logic
  • cpu mostly works, needs some more opcodes!

2013/10/02 - Howdy Simulator

  • Implemented ram
  • Added delays for ram

2013/09/25 - Verilog at last

  • Spec now has vsync
  • Reviewed sdlcore code
  • Hacked together some very basic Verilog

2013/09/18 - Let there be code

  • Debugged & Finished sdlcore implementation

2013/09/11 - September reunion

  • Discuss and improve specs a bit
  • Update documentation and C# ref. implementation
  • forked from Programmable Logic Lessons to Simple SoC

Resources