Simple SoC

Description

A very basic, custom SoC softcore



Primary git repo: on github

Specs/Design: on github as well

We'll merely keep a meetup log and notes here, important stuff will be stored in One Single Repo (tm), next to the code :)

Meetups

Upcoming

2014/01/15 - ICEful modules

  • Modularization, refactoring, and ice state



Log

2013/12/11 - Debuggable Hardware

  • Work on the ICE implementation



2013/12/04 - Clocks and IO

  • Worked around the IO/DCM issues
  • WIP on the ICE implementation

2013/11/20 - Want some ICE?

  • *almost* implemented the UART
  • We have some pin collisions on clock vs dcm vs io-standards per bank

2013/11/13 - Differential debugging

  • Investigate serial communications
  • Try out UART sample
  • draft out ICE spec

2013/10/30 - Corrupted Pixels

  • Had no luck actually locating the vga corruption bug
  • simulator results and simpler test cases seem to work fine
  • implemented wait

2013/10/23 - We love glitches

  • Fixed VGA, centered image, still outputs corrupted data though
  • vram resized to 256x256x3 in order to fit

2013/10/16 - How about conditions?

  • Implemented beq, bga, bgt, jr, draw, fixed write16, read16
  • wired up vram (resized to 2bpp because it doesn't fit)
  • added vga output, but it is glitched/buggy

2013/10/09 - Howdy Simulator, for real

  • debug, debug, debug, and simulate
  • Implemented more state logic
  • cpu mostly works, needs some more opcodes!

2013/10/02 - Howdy Simulator

  • Implemented ram
  • Added delays for ram

2013/09/25 - Verilog at last

  • Spec now has vsync
  • Reviewed sdlcore code
  • Hacked together some very basic Verilog

2013/09/18 - Let there be code

  • Debugged & Finished sdlcore implementation

2013/09/11 - September reunion

  • Discuss and improve specs a bit
  • Update documentation and C# ref. implementation
  • forked from Programmable Logic Lessons to Simple SoC

Resources